Mentor, a Siemens business, today announced in collaboration with Samsung Electronics that a wide range of Mentor design and verification tools and flows have been enabled for Samsung’s 8LPP process technology. The 8LPP provides the most competitive scaling benefit before the extreme ultraviolet (EUV) lithography era, with an additional performance boost compared to the 10LPP process. 8LPP tool enablement includes the Calibre® physical verification suite, Mentor® Analog FastSPICE™ (AFS™) custom and analog/mixed-signal (AMS) circuit verification platform, and Nitro-SoC™ place and route (P&R) digital design platform. These Mentor solutions are available for use in the design and sign-off of production tapeouts for Samsung 8LPP process technology.
In addition, core components of the Calibre suite have been enabled for the Samsung 7LPP process technology using EUV lithography, including Calibre nmDRC™, Calibre nmLVS™, Calibre xACT™, and Calibre PERC™ software. These Calibre design kits can be used for initial test chips and intellectual property (IP) creation on the Samsung 7LPP process technology.
“Samsung Foundry continues to offer the most competitive process technology in the industry. Our collaboration with Mentor ensures the availability of qualified tools that enable our mutual customers to develop designs that best leverage the Samsung Foundry’s process offerings,” said Jaehong Park, senior vice president of the Foundry Design Team at Samsung Electronics. “The Mentor tool enablement for our 8LPP and 7LPP is a demonstration of our long-term partnership that continuously strives to enable designers to implement, verify, test, and deliver designs with confidence.”
Samsung has enabled multiple tools in the industry-leading Calibre platform for the 8LPP process technology to ensure designers can achieve tapeout success quickly and confidently.
To enable system-on-chip (SoC) designers to complete circuit verification, physical implementation, and IC test with confidence, the AFS platform is enabled in Samsung’s 8LPP device models and design kits. Our mutual customers rely on the AFS platform to deliver nanometer SPICE accuracy while verifying analog, RF, mixed-signal, memory, and custom digital circuits faster than with traditional SPICE simulators.
The Nitro-SoC P&R system is enabled for netlist-to-GDSII physical implementation in the Samsung 8LPP process technology. A wide range of innovative technologies, including advanced design rule checking (DRC) avoidance on multi-patterning routing layers, mask and layer optimization for convergent timing, and smart library pin access capabilities are supported for optimized power/performance/area (PPA) results on this technology node. Customers have access to features like multi-corner multi-mode (MCMM)-based area optimization, comprehensive multi-VDD-based low power flow, native integration with Calibre sign-off, and comprehensive parallelization for a faster turnaround time.
“Our partnership with Samsung Foundry is not just a matter of providing tools that meet minimum requirements,” stated Joe Sawicki, Vice President and General Manager of the Mentor Design-to-Silicon Division. “The joint solutions we deliver enable our mutual customers to fully leverage Samsung’s process offerings for success in both initial tapeouts and silicon production, providing a vital link between fabless companies and Samsung Foundry.”