Инновации и синхронизированное управление совместной работой над проектами
Mentor, a Siemens business, today announced the availability of the ATE-Connect™ technology in its Tessent™ SiliconInsight™ product for IC debug and bring-up. The ATE-Connect technology creates an industry-standard interface to eliminate communication barriers between proprietary, tester-specific software and design-for-test (DFT) platforms. The new technology accelerates debug of IJTAG devices, helps speed up product ramps, and reduces time-to-market for products in 5G wireless communications, autonomous driving, and artificial intelligence. Mentor has also announced that Teradyne’s UltraFLEX test solution fully supports the new Mentor interface through its PortBridge technology.
Despite broad industry adoption of the IJTAG (IEEE 1687) test architecture for chip-level testing, many companies maintain very different approaches for converting chip-level test patterns into tester formats, as well as for debugging tests on automatic test equipment (ATE). Consequently each specific chip must have test patterns written by DFT engineers, and then translated by test engineers to debug each scenario on each tester type. Test engineers typically work at a low, detailed level with clock cycles, while DFT engineers work at a higher level using IJTAG. The differences in tools and techniques between the two can lead to confusion on how to most efficiently debug chips, resulting in long delays in the IC product lifecycle.
Using the TCP/IP network protocol, the Mentor ATE-Connect technology provides IJTAG commands to the device under test and receives data from the device on the ATE – all while keeping the sensitive design information in the realm of the Tessent SiliconInsight tool and only providing the required stimulus to the device under test on the ATE. With this standard network communication, customers can leverage their existing secure networks to enable seamless interaction with testers around the globe.
“Our customers demanded a better solution to the silicon bring-up challenge,” said Brady Benware, senior marketing director for the Tessent product family at Mentor, a Siemens business. “Directly linking the power of IJTAG with the ATE has eliminated a significant bottleneck in their debug and characterization processes. With this solution, customers can potentially achieve silicon bring-up in days instead of weeks.”
In addition to introducing ATE-Connect, Mentor’s Tessent division also announced it worked with Teradyne and key customers to validate the complete solution. Teradyne is a leading supplier of automation equipment for test and industrial applications. Mentor’s Tessent toolset with ATE-Connect coupled with Teradyne PortBridge on the UltraFLEX solution enables significant test debug productivity improvements because it enables a DFT development environment to communicate directly with the Teradyne UltraFLEX for interactive debug of an IP block.
"Teradyne is meeting our customers’ demands for increased productivity through a variety of innovative tools and partnerships,” said Jason Zee, vice president and general manager of SoC Business Group, Teradyne Semiconductor Test Division. “The partnership with Mentor is an important example of how we collaborate with our ecosystem partners to ensure our customers' success."
The first live interactive demonstration will be shown publicly at the International Test Conference, October 30 - November 1, 2018, Phoenix Convention Center, Phoenix, AZ. To learn more about the ATE-Connect technology in the Tessent SiliconInsight product, visit https://www.mentor.com/products/silicon-yield/products/silicon-insight.