Инновации и синхронизированное управление совместной работой над проектами
Wilsonville, OR, April 20, 2017 - Mentor, a Siemens business, today announced new formal-based technologies in the Questa Verification Solution that provide RTL designers and verification engineers with the ability to more easily perform exhaustive formal verification analysis. The new interactive multi-platform graphical user interface (GUI) for the Questa PropCheck and Questa CDC apps enables users to be productive anywhere. The Questa Verification Solution now also offers formal-based RTL-to-RTL equivalence checking flows with the Questa Sequential Logic Equivalence Checking (SLEC) app, which can reduce verification turnaround time by 10X. The app also offers expanded clock domain crossing (CDC) capabilities with the Questa CDC-GL app for gate-level CDC analysis to help avoid costly re-spins and ensure critical synchronization logic has not been disrupted.
New GUI Workflow Cuts Debug Cycle by 5x
Interactive debug capabilities are invaluable for shortening every step of the debug cycle—from failure detection to identification of the root cause of failures to development and validation of a fix. Using Mentor’s high performance Visualizer™ Debug Environment (itself built on the popular “Qt” platform), the Questa PropCheck app for formal verification enables users to more rapidly find root cause issues with their device under test (DUT) that the formal algorithms identify.
Additionally, with the industry-first web browser and mobile views, users can check on the progress of running jobs and analyze results when away from their workstations, enabling them to keep their projects on track 24/7. Using their employer’s VPN to provide a secure data link, users can access formal or CDC results and decide whether to re-run an analysis with new parameters, alert colleagues in different time zones to necessary corrective actions, or login to their employer-provided laptops to take more extensive corrective actions themselves.
10x Reduction to Popular Verification Flow with Exhaustive Sequential Logic Equivalency Checking
Even the most carefully designed testbench is inherently incomplete, since constrained-random methods cannot hit every corner case. Even after 100% functional coverage is achieved, there can still be showstopper bugs hiding in unimagined state spaces. Furthermore, many high-value verification tasks can take weeks of testbench development and simulation. In contrast, a host of verification use cases can be addressed by sequential logical equivalence checking in hours—even minutes—with exhaustive results.
Leveraging Questa PropCheck technology, the new Questa SLEC app provides an exhaustive comparison between the behaviors of two RTL blocks so users can be assured all possible corner cases have been checked. In particular, this app is optimized to address three popular RTL-to-RTL sequential equivalence checking flows: verification of manual low-power clock gating, bug fix and engineering change order (ECO) validation, and ISO 26262 safety mechanism verification.
“Our products can’t compromise on safety, so our verification must be to 100% complete,” says Thorsten Ehrenberg, Manager Safety Microcontroller Development of Continental’s division Chassis & Safety. “As such, formal-based verification solutions are essential given the exhaustive nature of the analysis. For some, IP Blocks formal verification is the only option to perform a complete verification. With the Questa SLEC formal app, it is possible to quantify the fault coverage of certain IP Blocks e.g. safety critical IP Blocks."
This new product complements the Calypto SLEC Pro and SLEC System offerings, which are focused on the verification of PowerPro™’s automatic power reductions and C-to-RTL equivalence checking respectively. In contrast, Mentor’s FormalPro™ solution will continue to focus on cases where the DUTs being compared have the exact same number of states (post-synthesis RTL-to-gate, and gate-to-gate logic equivalency checking).
New CDC Gate-level Analysis Prevents Chip-Killing Metastability
CDC bugs from clock signal metastability are impossible to detect with simulation. Without CDC analysis, CDC bugs will only be discovered in the lab, when it is too late to take corrective action other than to re-spin the whole chip. Even worse, at the gate-level of logic in advanced node devices (28 nm or lower), RTL CDC tools cannot easily detect glitches introduced by synthesis or other back-end tools on CDC paths that were safe at RTL.
The new Questa CDC-GL app is optimized for gate-level analysis. The app leverages the RTL CDC data and the waivers generated at the RTL level by the Questa CDC solution to produce focused “low noise” results that enable rapid identification of chip-killing gate-level CDC errors. The Questa CDC-GL app is ideally suited for designs at the 28nm node and below where a gate-level analysis approach is required to prevent nasty surprises when the initial samples come back from the fab.
All of these products are available immediately, with pricing dependent on product configuration.
Mentor Graphics, Mentor, Questa and SLEC are registered trademarks and Visualizer, PowerPro and FormalPro are a trademark of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owner.