01 May 2018

Mentor enhances tool portfolio for TSMC 5nm FinFET and 7nm FinFET Plus processes and Wafer-on-Wafer stacking technology

Mentor, a Siemens business, has announced that several tools in its Calibre® nmPlatform and Analog FastSPICE (AFS™) Platform have been certified by TSMC for the latest versions of TSMC’s 5nm FinFET and 7nm FinFET Plus processes. Mentor also announced it has updated its Calibre nmPlatform tools in support of TSMC’s Wafer-on-Wafer (WoW) stacking technology. These Mentor tools and TSMC’s new processes will enable mutual customers to more quickly deliver silicon innovations in high-growth markets.

“Mentor continues to increase its value to the TSMC ecosystem by offering more features and solutions in support of our most advanced processes,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “By continuing to innovate leading-edge electronic design automation (EDA) technologies for our new processes, Mentor is again proving its commitment to TSMC and our mutual customers.”

Mentor’s enhanced tools for TSMC 5nm FinFET and 7nm FinFET Plus processes
Mentor worked closely with TSMC to certify various tools in Mentor’s Calibre nmPlatform – including Calibre nmDRC™, Calibre nmLVS™, Calibre PERC™, Calibre YieldEnhancer, and Calibre xACT™ – for TSMC’s 5nm FinFET and 7nm FinFET Plus processes. These Calibre solutions now have new measurements and checks including, but not limited to, supporting extreme ultraviolet (EUV) lithography requirements jointly defined with TSMC. Mentor’s Calibre nmPlatform team is also working with TSMC to address physical verification runtime performance by enhancing scalability of multi-CPU runs to improve productivity. Mentor’s AFS platform, including the AFS Mega circuit simulator, is also now certified for TSMC’s 5nm FinFET and 7nm FinFET Plus processes.

Mentor’s enhanced tools for TSMC’s WoW stacking technology
Mentor made enhancements to its Calibre nmPlatform tools in support of the WoW packaging. Enhancements include DRC and LVS signoff for dice with backside through-silicon vias (BTSV), interface alignment and connectivity checks for die-to-die as well as die-to-package stacking. Further enhancements include parasitic extraction on backside routing layers, interposers with through-silicon vias (TSVs), and interface coupling.

Calibre Pattern Matching for TSMC’s 7nm SRAM Array Examination Utility
Mentor worked closely with TSMC to integrate Calibre Pattern Matching into TSMC’s 7nm SRAM Array Examination Utility. This flow helps customers to ensure their SRAM implementations are constructed to meet process requirements. This automation enables customers to tape out successfully. The SRAM Array Examination Utility is available to TSMC’s customers for 7nm production. 

“TSMC continues to develop innovative silicon processes that enable our mutual customers to bring to market many of the world’s most advanced ICs,” said Joe Sawicki, vice president and general manager of the Design-to-Silicon Division at Mentor, a Siemens business. “We, at Mentor, are proud to not only lead the way in certifying our platforms for TSMC’s latest processes, we are also proud of our close partnership with TSMC in developing new technologies that help customers achieve production silicon faster.”

To learn more, visit Mentor at booth #408 at TSMC’s Technology Symposium on May 1, 2018 at the Santa Clara Convention Center in Santa Clara, California.

Główny kontakt

Jack Taylor