18 May 2015

Mentor Graphics Tessent Hierarchical ATPG Solution Selected by Mellanox Technologies for Giga-gate Designs

WILSONVILLE, Ore., May 18, 2015—Mentor Graphics Corp. (NASDAQ: MENT) today announced that Mellanox Technologies has standardized on the new Mentor® Tessent® Hierarchical ATPG solution to manage the complexity and slash the cost of generating test patterns for their leading-edge integrated circuit (IC) designs. Using Tessent hierarchical ATPG, Mellanox has significantly reduced both the processing time and system memory needed to generate the huge number of manufacturing test patterns needed for high-quality IC test.

“The time needed to generate test patterns has been growing rapidly with each new design cycle, thus increasing our test-related costs,” said Evelyn Landman, VP of Backend Engineering at Mellanox Technologies. “Moving to Mentor’s Tessent hierarchical ATPG flow has allowed us to significantly reduce turnaround time on current designs. Because this solution is highly scalable, we expect to continue using it on our future designs.”

The Tessent hierarchical ATPG flow uses a divide-and-conquer approach to break down the overall ATPG task into smaller, more manageable pieces. Compressed patterns are first generated for each design core in isolation, then automatically retargeted to the chip level and merged to minimize test time. Compressed patterns are then generated for top-level interconnect and glue logic. This process removes the final DFT and compute-intensive pattern generation steps from the critical tape-out path, adding predictability to the test flow.

The hierarchical ATPG approach significantly reduces runtime and memory footprint compared to running ATPG for all blocks and interconnect at the top level. Reductions in runtime in the range of 5x-10x are typical, and memory footprint savings can be even greater. Hierarchical ATPG often reduces pattern count (and consequently test time) by as much as 2x due to increased efficiency in how scan channels are used across all of the cores.

“Many of our customers are using hierarchical design methodologies to manage the size and complexity of their designs. It has become clear to most of them that their test generation flow has to mirror this hierarchical approach,” said Stephen Pateras, product marketing director for Mentor’s Tessent DFT and ATPG products. “Our new hierarchical ATPG solution is not only scalable for 100M+ gate designs, but it helps improve schedules by allowing DFT and ATPG to be moved earlier in the design cycle and to be more easily distributed among different groups.”

(Mentor Graphics, Mentor, and Tessent are registered trademarks of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.)

대표 문의처

David Smith
503.685.1135
david_smith@mentor.com