Place and Route

As designs increase in complexity, the place and route design phase is often performed by electronic design automation (EDA) tools. These tools create the best possible design within the prioritized constraints quickly and reliably.
A circuit board, with a processor at the center

Place and route software tools for complex SoC designs

Place and route software tools help designers meet optimization goals for power consumption and performance for system on a chip (SoC) designs. These complex integrated circuits typically include computer components and are commonly found in mobile devices such as smartphones.

Place and Route in VLSI Design

The process of very-large-scale integration (VLSI) design involves combining millions of Metal Oxide Semiconductor (MOS) transistors on a single chip to create an integrated circuit (IC). These complex chips provide integrated functions for high-performance computing, telecommunications, and consumer electronics. Single chip integrations provide compactness, less power consumption, fewer system tests, higher reliability, and higher speed. Place and route in complex VLSI design involves placing the cells and connecting them to meet the design power, performance, and area (PPA) goals. 

Place and Route for Low Power

The integrated circuit (IC) community uses power, performance, and area (PPA) to refer to key areas of focus in optimizing an integrated circuit (IC). Performance is typically optimized over power and area, but as designs move to smaller, more advanced process nodes, power is growing in importance. Many challenges of achieving low power during place-and-route (P&R) relate to how well the P&R software handles multiple power domains and the kinds of optimizations the software performs throughout the flow to achieve low power goals.