WILSONVILLE, Ore., March 15, 2017—Mentor Graphics Corp. (NASDAQ: MENT) today announced that TSMC has certified the Calibre® Platform (Calibre nmDRC™, Calibre Multi-Patterning, Calibre nmLVS™, Calibre YieldEnhancer with SmartFill, and Calibre xACT™ tools), as well as the Analog FastSPICE (AFS™) Circuit Verification Platform, for the most current version of the 12FFC process. In addition, the Calibre Platform (Calibre nmDRC, Calibre Multi-Patterning, Calibre nmLVS, Calibre PERC™, and Calibre YieldEnhancer with SmartFill tools), the Nitro-SoC place and route (P&R) Platform, and the AFS Platform have been certified for the TSMC 7 nm V1.0 process.
The Calibre enablement suite is now available for the latest TSMC 12FFC process for customers’ designs. In addition, the AFS Circuit Verification Platform, including AFS Mega, has achieved readiness for 12FFC technology and TSMC Modeling Interface (TMI) support.
For TSMC 7 nm, the full Calibre enablement has been updated to the V1.0 release level for customers’ production design tapeouts. Throughout the various releases, TSMC and Mentor have worked to continuously improve Calibre DRC runtimes. The current V1.0 release has shown a significant runtime improvement compared with the initial releases.
Reliability is a critical success factor in many of today’s electronics. TSMC and Mentor Graphics expanded their collaboration to the 7 nm process for comprehensive verification of electrostatic discharge (ESD) and latch-up issues that can affect reliable performance and product lifetime. This collaboration led, in part, to the development of a multi-CPU capability in the Calibre PERC tool that can be used for full point-to-point (P2P) resistance and current density (CD) checking.
Engineering change orders (ECOs) usually arrive late in the process flow, and often disrupt tapeout schedules. To accelerate our mutual customers’ ability to achieve design closure, TSMC and Mentor Graphics partnered to expand the Calibre YieldEnhancer ECO fill flow from 20 nm down to the latest 7 nm technology. The ECO fill flow allows customers to quickly manage late-stage design changes while ensuring the changes remain in compliance with TSMC’s manufacturing requirements.
The AFS Platform, including the AFS Mega circuit simulator, has been certified for the TSMC 7 nm V1.0 process. Analog, mixed-signal, and RF design teams at leading semiconductor companies worldwide benefit from using the AFS platform to efficiently verify their chips designed in the latest TSMC technologies.
Mentor’s Nitro-SoC P&R Platform was enhanced to meet all TSMC 7 nm design enablement and certification requirements. Mentor also demonstrated its 7 nm readiness by the successful implementation of the ARM processor using the Nitro-SoC P&R Platform, which is now ready for customer deployment.
“Our ongoing collaboration with Mentor Graphics ensures that the EDA solutions and services our mutual customers need for successful manufacturability at every node are available and supported,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division, TSMC. “By working together, we combine the expertise of both companies to enable our customers’ success.”
“The partnership we enjoy with TSMC is critical not only in identifying the challenges new technologies bring, but also in developing solutions that ensure our joint customers can take advantage of the benefits of that new technology, while still delivering designs that are in compliance with TSMC’s manufacturing requirements,” said Joseph Sawicki, vice president and general manager of the Design to Silicon division at Mentor Graphics. “Our customers’ success is the definition of our success.”
(Mentor Graphics, Mentor, and Calibre are registered trademarks and nmDRC, nmLVS, PERC, xACT, and AFS are trademarks of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.)