Samsung’s 8LPP process reference flow leverages Mentor Tessent tools for large design test-time savings

Mentor, a Siemens business, today announced that Samsung Electronics Co., Ltd., has certified the Mentor Tessent® products for Samsung Foundry’s 8-nanometer (nm) LPP (Low Power Plus) process. These tools provide dramatic design and test time improvements for very large designs targeting markets such as mobile communications, high-speed network/server computing, cryptocurrency, and autonomous driving.

Very large designs in today’s leading semiconductor devices can suffer from requiring large compute resources, and pattern-generation times that are too long or are being performed too late in the design flow. The Tessent TestKompress® tool solves these issues by providing automated capabilities with a hierarchical design-for-test (DFT) methodology. The Samsung Foundry Solutions reference flow includes TestKompress scan compression logic and Tessent ScanPro on-chip clock controllers automatically inserted early in the register transfer level (RTL) design stage. Tessent TestKompress is used to create patterns at the core-level, early in the design flow as soon as the core design is ready. These patterns are directly reused and retargeted to the full chip design automatically. As a result, compute resources for automatic test pattern generation (ATPG) and ATPG run times can be improved by an order of magnitude. A full device netlist is not needed in the Tessent hierarchical DFT flow.

“Of those processes introduced before the EUV era, our 8LPP is the best choice in terms of performance, power and area,” said Ryan Lee, vice president of Foundry Marketing at Samsung Electronics. “Our long-term collaboration with Mentor will make our 8LPP more attractive to our mutual customers. Mentor’s Tessent TestKompress hierarchical DFT solution is an example of a technology that will provide dramatic savings in test generation turnaround time.”

The Tessent TestKompress tool is used to share scan data inputs to design cores in MCP (Multi-Core Processor) designs. Sharing input pins enables higher levels of pattern compression, which correlates to lower production test costs. The Tessent Diagnosis and Tessent YieldInsight® tools are used to find systematic yield limiters and improve fabrication yields. These tools include automation to perform reverse-pattern mapping, so failing production patterns directly map to the hierarchical block to which they relate. Performing diagnosis on a targeted block improves diagnosis time and compute resource size by an order of magnitude.

“The larger and more complex designs that are made possible with Samsung Foundry’s 8LPP require additional DFT and automation to meet time-to-market and cost-of-test requirements,” said Brady Benware, director of marketing for the Tessent product family at Mentor. “Key capabilities in this reference flow, like hierarchical DFT, are being widely adopted in the industry and are essential for success with this new process technology.”

For more information on Tessent solutions, visit https://www.mentor.com/products/silicon-yield/tessent/.