Mentor certified for latest TSMC 5nm FinFET process and innovative TSMC-SoIC 3D chip stacking technology

Mentor, a Siemens business, today announced that several tools in its Calibre™ nmPlatform and Analog FastSPICE (AFS™) Platform have been certified on TSMC’s 5nm FinFET process technology. Mentor also announced it has successfully completed reference flow materials in support of TSMC’s innovative System-on-Integrated-Chips (TSMC-SoIC™) multi-chip 3D stacking technology. 

“Mentor has yet again increased its value to TSMC’s ecosystem by offering more features and solutions in support of our most advanced process,” said Suk Lee, TSMC senior director, Design Infrastructure Management Division. “The collaborative efforts combining Mentor’s tools with TSMC’s industry-leading process can enable our mutual customers to quickly launch their silicon innovations in high-growth markets, including smart mobile and high-performance applications.”

Mentor’s enhanced tools for TSMC’s 5nm FinFET process
Mentor worked closely with TSMC to certify its Calibre nmDRC™, Calibre nmLVS™, Calibre YieldEnhancer, Calibre PERC™ and AFS Platform software on TSMC’s 5nm FinFET process for the benefit of mutual customers. For example, Mentor’s Calibre PERC reliability verification solution on TSMC’s 5nm FinFET technology is engineered to help enhance product reliability by making leakage checks available for full chip designs. Running these checks can help mutual customers ensure that excess leakage is avoided for optimal design performance.

In addition, Mentor’s AFS Platform certification for TSMC’s most advanced process allows Mentor customers targeting analog, mixed-signal and radio frequency (RF) designs to verify their chips with confidence on TSMC’s 5nm FinFET process.

Mentor’s enhanced tools for TSMC’s innovative SoIC 3D chip stacking technology
Mentor has also successfully completed reference flow materials for key elements of its Calibre nmPlatform and Xpedition™ IC Packaging design flow software in support of TSMC’s advanced SoIC technology. TSMC’s innovative SoIC technology supports stacking of multi-chips using chip-on-wafer bonding process, and provides a bumpless bond structure to enable better performance. Mentor’s support for this advanced TSMC chip stacking technology includes the use of Xpedition Substrate Integrator (XSI) software for design planning and netlist management, Calibre 3DSTACK tools for physical verification, and the Calibre xACT™ solution for parasitic extraction between dies. With recently added ability to cross-probe Calibre 3DSTACK results to XSI, debug and iteration time can be greatly reduced.

“Mentor is pleased to collaborate with TSMC to continue to deliver innovative technologies that enable our mutual customers to bring to market many of the world’s most advanced ICs,” said Joe Sawicki, executive vice president for Mentor’s IC Segment. “This year, TSMC and Mentor are jointly delivering solutions that provide our mutual customers with multiple design options to choose from to quickly deliver ICs that differentiate in fast-growing and highly competitive markets.”