Mentor’s Tessent VersaPoint test point technology helps Renesas reduce cost and improve quality

Mentor, a Siemens business, today announced the availability of the VersaPoint™ test point technology in its Tessent® ScanPro and Tessent LogicBIST products, which maintain ISO 26262 qualification. The VersaPoint test point technology reduces manufacturing test cost and improves quality of in-system test – two critical requirements for high-reliability ICs in the automotive and other industries. Mentor is also announcing that Renesas Electronics has adopted the VersaPoint technology for its automotive ICs to address safety-critical test requirements in order to reach Automotive Safety Integrity Level (ASIL) C and D certification.

Digital circuitry in automotive ICs is commonly tested using a hybrid of on-chip compression/ATPG and logic built-in self-test (LBIST) technologies to achieve very high defect coverage for manufacturing test, and enable in-system and power-on self-test.

Test points are dedicated design structures used to improve the test results. Traditional LBIST test points improve results by addressing “random pattern resistance” in ICs. Mentor more recently developed test points specifically for on-chip compression/ATPG, which reduces ATPG pattern count by 2-4X above what is achieved with on-chip compression alone. The Tessent VersaPoint test point technology combines and improves upon these technologies.

“To deliver industry-leading automotive ICs, Renesas uses test points to help us meet our strict IC test requirements,” said Hisanori Ito, Vice President, Automotive SoC Business Division at Renesas Electronics Corporation. “With the Tessent VersaPoint test point technology, we no longer need separate solutions for different types of ICs. As a result, we see improved quality and reduced cost in both manufacturing and in-system tests. The simplified DFT implementation flow also shortens development cycles and accelerates time-to-market.”

Tessent VersaPoint technology results in higher LBIST test coverage compared to traditional LBIST test points, and better ATPG pattern count reduction than when using on-chip compression/ATPG test points. This technology is designed for test engineers using Tessent Hybrid ATPG/LBIST to improve cost and quality of test, particularly for ICs targeting automotive applications.

“Our customers are continuously looking to reduce their test costs as their design sizes grow and quality requirements become more stringent,” said Brady Benware, Director of Marketing for the Tessent Product Family at Mentor. “At the same time, there is an increased demand for efficient in-system test in high-reliability applications. With the VersaPoint test point technology, our customers have a more effective way of meeting both manufacturing and in-system test requirements.”