Mentor extends solutions to support TSMC 5nm FinFET and 7nm FinFET Plus process technologies

Mentor, a Siemens business, today announced certification for TSMC’s 7nm FinFET Plus and the latest version of 5nm FinFET processes for its Mentor Calibre® nmPlatform and Analog FastSPICE™ (AFS™) Platforms. In addition, Mentor continues to expand features of both the Xpedition™ Package Designer and Xpedition Substrate Integrator products supporting TSMC’s advanced packaging offerings.

“TSMC is working closely with Mentor, which continues to increase its value to the TSMC ecosystem by offering more features to its EDA solutions in support of our new 5nm and 7nm FinFET Plus processes,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “Mentor has been a strategic partner for many years, and with Siemens' continued strategic investments in Mentor's electronic design automation (EDA) technologies, they are helping our mutual customers be even more successful in bringing to market the next generation of amazing IC innovations.”

Mentor Calibre nmPlatform for TSMC 5nm and 7nm FinFET Plus
Mentor enhanced the Calibre nmDRC™ and Calibre nmLVS™ tools for TSMC’s 7nm FinFET Plus process and the latest version of 5nm FinFET process. Mentor continues to provide the functionality and performance that TSMC customers need to achieve their manufacturing requirements. The Calibre nmDRC and Calibre nmLVS tools are cloud-ready, and they are in deployment on thousands of CPU-count server solutions with customers today.

Mentor’s Caliber YieldEnhancer tool is certified for TSMC’s 5nm and 7nm FinFET Plus processes. Mentor and TSMC developed unique fill routines, which achieve manufacturing requirements by tightly controlling the location of the fill shapes. The combination of the Calibre YieldEnhancer tool’s capabilities and TSMC’s Calibre Fill Design Kit maximize the insertion rate.

The Calibre PERC™ reliability platform is not only certified for TSMC’s 5nm and 7nm FinFET Plus processes, it has newly enhanced TSMC-developed PERC constraint checks to enable TSMC’s customers to improve the reliability of their designs.

Mentor’s enhanced tools for TSMC’s InFO_MS stacking technology
Mentor continues to enhance its tool set in support of TSMC’s InFO_MS (Integrated Fan-Out with Memory on Substrate) advanced stacked packaging offering. In addition to its ability to create and manage complex inter-component connectivity, and as key automation to Xpedition Package Designer for layout, Mentor’s Xpedition Substrate Integrator has been extended to enable automation for source net list generation for running Calibre 3DSTACK for connectivity checking. The Calibre 3DSTACK™ for LVS, Calibre nmDRC, Calibre xACT for interface coupling capacitance extraction, and Calibre PERC tools for point-to-point (P2P) checks are also part of TSMC’s InFO_MS reference flow. These enhancements provide comprehensive implementation and verification solutions to the TSMC InFO_MS design flow.

Mentor AFS Platform for TSMC 5nm FinFET and 7nm FinFET Plus
The AFS platform, including the AFS Mega circuit simulator, is certified for TSMC’s 7nm FinFET Plus process and the latest version of 5nm FinFET process. Analog, mixed-signal and radio frequency (RF) design teams at leading semiconductor companies worldwide benefit from using the AFS platform to verify their chips designed in the latest TSMC technologies.

“Mentor is proud to collaborate with TSMC to continue to deliver linchpin technologies so in turn our customers can bring to market IC innovations more quickly,” said Joe Sawicki, executive vice president for Mentor’s IC Segment. “This year, TSMC and Mentor are jointly delivering solutions that provide our mutual customers with an expanding number of design avenues so they can quickly deliver ICs for the mobile, high-performance computing, automotive, AI and IoT/wearable markets.”