Innovación y gestión de programas colaborativa y sincronizada para nuevos programas
WILSONVILLE, Ore., June 3, 2015 - Mentor Graphics Corp. (NASDAQ: MENT) today announced that United Microelectronic Corporation (UMC) is developing an IC reliability reference flow for its customers based on the Calibre® PERC™ reliability verification platform. The new flow will help customers improve the long-term reliability of their IC products by detecting subtle design flaws, such as missing electrostatic discharge (ESD) protection circuits that can cause in-field failures. The solution includes predefined checks that are jointly being developed by UMC and Mentor Graphics, which is targeted for all mutual customers using UMC’s 28nm manufacturing processes. An initial release of reliability checks is targeted to be released by UMC towards the end of this year.
UMC and Mentor will preview the planned offering at this years Design Automation Conference in San Francisco, CA. The joint presentation will be Wednesday, June 10, at 2:00PM in the Mentor booth (1432). The information will be presented in Mandarin as well as English.
UMC is also adding the Calibre RealTime solution to their design enablement offerings. UMC simulations using the Calibre RealTime tool have experienced 2X or greater productivity improvement in finding and addressing physical verification issues while doing custom design. The Calibre RealTime tool will allow designers to see verification errors interactively as they are creating circuits in their preferred layout editor. Since the tool uses UMC’s golden signoff Calibre design kits, UMC customers will also be able to enjoy the same productivity enhancements documented by UMC.
“Circuit reliability checking requires specialized tool capabilities,” said Shih Chin Lin, director of IP Development and Design Support at UMC. “Designers need automated support to identify specific structures like ESD protection circuits, and to calculate internal voltage values to make sure that voltage limits are maintained at every node in the circuit. At the same time, improved productivity is always welcomed by design teams inside of UMC and by UMC’s customers. By adding Calibre PERC and Calibre RealTime to our design enablement offering, we will be able to address both of these needs.”
The Calibre PERC solution provides unique functionality that enables checks based on information from both the physical layout and the schematic netlist, which defines device types and connectivity. This Logic-Driven-Layout (LDL) analysis capability ensures that all designs, including UMC IP libraries and customer designs, conform to UMC’s enhanced ESD and electrical overstress (EOS) design rules. Some of the key ESD/EOS protection techniques include:
The Calibre PERC product, working in concert with the rest of the Calibre platform, detects violations of the reliability design guidelines and also helps designers debug circuit reliability problems by providing a comprehensive view of circuit connectivity, topology, physical layout and design rules.
“UMC and Mentor have pooled their experience and collaborated on an automated solution that makes it easier for designers to ensure they have a state-of-the-art design for reliability, along with greatly improved design verification productivity,” said Michael Buehler-Garcia, senior director of Calibre Design Solutions marketing at Mentor Graphics. “With the growing emphasis on both electronics reliability and shorter design development timelines in automotive, medical and other markets, having both Calibre PERC and Calibre RealTime in your IC toolbox is a critical advantage.”
UMC plans to expand the number of checks offered in future releases tied to various process node updates.
(Mentor Graphics, Mentor, and Calibre are registered trademarks and PERC is a trademark of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.)