Training Course

Introduction to System Verilog

This course will try to cover the entire System Verilog language with examples. It focuses on the features of the language:

  • Significant additions from Verilog
  • What are they used for
  • How are they used
  • Features that are useful for design and verification
  • Lab exercises using ModelSim/Questa

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This course will try to cover the entire System Verilog language with examples. It focuses on the features of the language:

  • Significant additions from Verilog
  • What are they used for
  • How are they used
  • Features that are useful for design and verification
  • Lab exercises using ModelSim/Questa