Mentor’s Veloce Strato emulation platform selected by Iluvatar CoreX for verification of AI chips and software

Mentor, a Siemens business, today announced that artificial intelligence (AI) silicon specialist Iluvatar CoreX has standardized on the Veloce™ Strato emulation platform for the verification of their AI cloud training system-on-chip (SoC) chipset and proprietary software platform. Founded in December 2015 to meet the growing demand for scalable, high-performance silicon solutions for the fast-growing AI space, Iluvatar CoreX delivers advanced intelligence for both edge devices and cloud-based applications.

“Iluvatar’s solution addresses limitations in current chip design by exploiting the advantages of an ultra-large-scale parallel computing architecture,” said Rachel Fan, vice president of R&D for Iluvatar CoreX. “Mentor’s Veloce virtual solutions, such as Veloce VirtuaLab PCIe and Veloce Protocol Analyzer, are a vital element of our verification environment, especially for hardware and software validation and debug.”

The emergence of AI presents a unique opportunity for disruptive semiconductor innovation, driven by fast-evolving end applications such as ADAS, 3D facial recognition, voice and image processing, and intelligent search. Among the challenges specific to successful AI chip development is the unique set of requirements that verifying these chip designs presents, including optimized scalability, determinism, virtualization, and 100 percent visibility for debug – all of which align with the Veloce emulator’s key strengths:

• Scalability: the Veloce Strato emulator scales from 40 million to 15 billion gates, allowing customers to develop large, highly sophisticated AI designs without compromising emulation performance or verification schedules.
• Virtualization: The Veloce Strato emulator can virtualize all the information required for design verification. Whether leveraging its library of verification components or using components from other sources, Veloce provides full visibility and freedom to control execution of the verification suite.
• Determinism: Veloce Strato emulators deliver fully deterministic functionality. When testing either hardware or software, customers can repeat runs over and over, probing hardware and single-stepping code until every aspect of the design’s behavior has been explored.
• Debug:  Complexity in IC design creates the need for extensive internal visibility into the design to understand subtle problems that occur during silicon bring-up. Veloce Strato emulators have sufficient execution speed, full-visibility capabilities and ease-of-use in model creation and model updates to span the entire range of debug needs throughout the life of the design development process.

“Veloce Strato continues to lead the way in the verification of AI chips,” said Eric Selosse, vice president and general manager of Mentor’s Emulation division. “We are pleased to add Iluvatar CoreX to our growing list of AI customers. Iluvatar’s highly innovative chip designs showcase the unique strengths and advantages Veloce provides for the verification of complex AI designs.”