19 November 2019

Graphcore leveraged Mentor’s Questa technologies to verify massive Colossus GC2 AI processor

Mentor, a Siemens business, has revealed that artificial intelligence (AI) processing leader Graphcore leveraged Mentor’s Questa™ software for simulation and verification of IP technologies to rapidly verify Graphcore’s massive Colossus GC2 Intelligence Processing Unit (IPU). Colossus has been shipping to early access customers for over a year and is now shipping in production volume.

Engineered to boost the performance of machine intelligence models for both training and inference, Graphcore’s Colossus IPU is one of the most sophisticated processors ever created. Featuring a novel architecture, Colossus integrates 23.6 billion transistors and more than 1,000 IPU-Cores.

To help streamline IC verification for this immense design, Graphcore selected Mentor’s Questa RTL simulation flow, in conjunction with Mentor’s Questa Verification IP (QVIP) solution for PCI Express. These Questa tools helped streamline Graphcore’s design productivity by providing rigorous protocol verification, while supporting efficient and highly compliant implementation of the SystemVerilog IEEE standard.

“Mentor’s Questa solutions delivered the capacity, tools, IP and trusted verification flow we needed for a design of this size and complexity,” said Phil Horsfield, vice president of Silicon at Graphcore. “The performance and capacity of Mentor’s Questa solutions allowed us to focus on our differentiating IP, which helped us deliver a truly unique and compelling end-product.”

Research firm IBS, Inc. estimates that AI-related applications consumed $65 billion (USD) of processing technology last year, growing at an 11.5 percent annual rate and significantly outpacing other segments. This processing demand has until now been supplied by microprocessors not fully optimized for high AI workloads.

Mentor’s Questa Sim simulation flow has a long track record of use in complex block- and chip-level testbenches for the register-transfer level (RTL) verification of some of the largest, most complex and highly successful silicon designs. Mentor’s QVIP solution provides an easy-to-use library of verification IP for more than 40 standard protocols and 1,700 memory devices. It includes checkers and coverage, plus a comprehensive set of stimulus sequences for the protocols.

“As demand for AI chips challenges the capacity and scalability of EDA software across all parts of the design flow, customers are choosing Mentor’s robust, proven tools to help bring their products to market,” said Ravi Subramanian, general manager and vice president of Mentor’s IC Verification Solutions. “Mentor is pleased to have played a significant role in development of one of the largest, most complex AI chips on the market today from Graphcore.”

In addition to leveraging Questa technology for verification tasks, Graphcore also used Mentor’s Tessent design-for-test (DFT) and silicon bring-up tools, helping Graphcore to deliver Colossus ahead of schedule.

Primary Contact

Jack Taylor

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