07 October 2016

Open-Silicon Extends Long-Term Collaboration with Mentor Graphics Technologies for Custom SoC Design Success

BANGALORE, India, October 07, 2016 - Mentor Graphics Corporation (Nasdaq: MENT) today announced that Open-Silicon, a system-optimized ASIC solutions company, has extended its long-standing deployment of Mentor’s physical verification and design-for-test (DFT) technologies for another three years. To date, Open-Silicon has successfully completed more than 300 ASIC/SoC designs using Mentor Graphics’ technologies. In addition, Open-Silicon is expanding its engagement with leading Mentor Graphics IC implementation solutions, like Calibre® xACT™, Calibre® Multi-Patterning and Calibre® YieldEnhancer, to address a number of key challenges in its custom SoC design projects at 14/16nm and for early development projects at 7nm. 

Open-Silicon has been able to achieve a quick turnaround time for GDS hand-off with Mentor’s chip finishing tool, Calibre® DESIGNrev™. Electrical reliability and robustness of its ASIC/SOC designs at 28nm and below are ensured using a plethora of programmable electrical rule checks available with Mentor Graphics Calibre® PERC™. The system-optimized ASIC solutions company has also been using Mentor’s Tessent® TestKompress® solution for advanced ATPG to reduce test pattern volume and test cost, and Mentor’s on-chip clock control logic to generate clocks for at-speed capture. Tessent® BoundaryScan and MemoryBIST are in use for testing embedded memories, and iJTAG solutions enable in-system test for SoCs. 

“The decision to continue our partnership with Mentor Graphics for another three years underscores our commitment to our robust Physical Verification, DFT and DFM methodology,” said Anam Haque, Vice President of Silicon Engineering for Open-Silicon. “Mentor’s industry-leading tools facilitate the validation of controls and checks critical to the process for shipping quality products. These best-in-class EDA tools are part of our overall engagement flow, and have been key to our success in completing over 300 designs successfully, and shipping over 120 million ASICs with very low DPPM (40 PPM), on time delivery (OTD)99% and negligible customer returns.”  

"In today’s challenging design world, long-term technology partnerships provide great value,” said Raghu Panicker, Country Sales Director, Mentor Graphics.  “We are extremely happy to extend this collaboration to accelerate Open-Silicon’s growth, innovation and technological excellence in the ASIC design world.” 

Primary Contact

Veeresh Shetty
+91-80-6762 4000