Imagination Technologies Adopts Mentor’s Oasys Physical Synthesis Platform to Reduce Design Cycle Time

WILSONVILLE, Ore., October, 11th  2016—Mentor Graphics Corp. (NASDAQ: MENT) today announced that Imagination Technologies (IMG.L), a leading multimedia, processor, and communications technologies company, has adopted Mentor® Oasys-RTL™ to help eliminate register transfer language (RTL) and floor planning bottlenecks and achieve optimal design performance, power and area goals.  The Oasys-RTL solution is in active use at Imagination and is the plan of record for select upcoming designs, demonstrating significant reduction in design cycle times and number of iterations.

Imagination’s PowerVR™ range of multi-standard video encode and decode IP cores offer performance scalability from single stream low-definition video decode acceleration to multi stream high-definition hardware video encode and decode. These video cores enable customers to create reliable multimedia system on chip (SoC) solutions where die size, power consumption, performance and adherence to standards are critical for success. Imagination takes advantage of innovative EDA solutions to help deliver a comprehensive intellectual property (IP) portfolio, reference platforms, subsystem IP cores, and ecosystem support to their customers and partners.

“We are designing some of the most complex IP cores in the world,” said Graham Deacon, Vice President, PowerVR Business Operations, Imagination. “We collaborated with Mentor to enhance our RTL design methodologies and are pleased with the results. On our most recent video cores, Oasys-RTL helped eliminate critical RTL bottlenecks early in the design cycle and significantly reduced the iterations late in the design cycle. We continue to work with Mentor to further improve the quality of our IP cores and improve the productivity of the SoC developers integrating our IP.”  

The Oasys-RTL solution is architected to meet the needs of complex, advanced node, high performance designs, with the capacity to handle 100+ million gates and up to 10X shorter runtimes. It integrates full chip-level physical synthesis, floor planning, and optimization at a higher level to enable RTL designers to accurately identify and resolve timing, routability, and power issues as soon as possible. The Oasys-RTL product includes the powerful ability to cross-probe between the physical and RTL databases, allowing RTL engineers to quickly and accurately identify the root cause of timing and congestion issues and resolve the problems early in the design cycle. It is the first tool to provide all the design views, from logical to physical to timing, in a single RTL synthesis platform. Its capacity and speed enables designers to perform parallel design space exploration of different design metrics, such as power, performance, and area. The Oasys-RTL solution’s Parallel Implementation Exploration feature provides the ability to actively explore design alternatives prior to implementation.

“Traditional synthesis solutions are plagued by capacity limitations and lack of floorplans during RTL design stages,” said Pravin Madhani, General Manager, IC Implementation Division, Mentor Graphics. “Our patented PlaceFirst technology enables customers to generate floorplans automatically from RTL during physical synthesis and to optimize at the RTL level instead of gate level, delivering the best power, performance and area results for the biggest designs in the shortest times. Our partnership with Imagination has resulted in the development of advanced technologies and different use models for the front and backend teams, leading to better quality of results and improved predictability throughout the flow.”  

For additional information, please visit:  Mentor.com/Oasys-RTL

(Mentor Graphics, Mentor are registered trademarks, and Oasys-RTL is a trademark of Mentor Graphics Corporation. Imagination Technologies and PowerVR are trademarks of Imagination Technologies Limited.  All other company or product names are the registered trademarks or trademarks of their respective owners.)