Advanced package design to manufacturing

Woman examining chip placement on board

In the 1920s, the island of Manhattan was facing a dilemma. They had run out of real estate, though the demand was still rising for offices and residences. They needed a new solution, so they decided to build high rises. Going vertical was the only way they could get enough capacity in the limited space.  

Today, the same problem is happening in the semiconductor industry. There is only so much space available on the real estate of a chip. We cannot keep miniaturizing to keep up with Moore’s Law, which says the number of transistors in a microchip doubles every two years. Just like Manhattan went vertical, now with Advanced Packaging Design we can stack layers higher in the package, but this shift puts different pressures on the design process that requires a new way of thinking.

In the 1920s, the island of Manhattan was facing a dilemma. They had run out of real estate, though the demand was still rising for offices and residences. They needed a new solution, so they decided to build high rises. Going vertical was the only way they could get enough capacity in the limited space.  

Today, the same problem is happening in the semiconductor industry. There is only so much space available on the real estate of a chip. We cannot keep miniaturizing to keep up with Moore’s Law, which says the number of transistors in a microchip doubles every two years. Just like Manhattan went vertical, now with Advanced Packaging Design we can stack layers higher in the package, but this shift puts different pressures on the design process that requires a new way of thinking.

Inside look of a semiconductor

Learn More

When semiconductor designers stack layers higher in the package to deliver more computing power in less space, no longer do we have just a flat chip with lots of transistors on it. Now we have a third dimension, so we must consider how that impacts the packaging equation. We are now mixing electronics and mechanical together as never before. Thermal stability and stress changes. So, there are some critical new factors to consider when doing that.

Critical factors to consider:

Off-the-shelf semiconductor relational data model

It is essential to virtually simulate and test the complete package assembly and design flow, including 3D IC, to predict performance, analyze viability, unleash the power of IP to consolidate learnings and accelerate smart decisions.

Integrated ECAD, MCAD, & CAE toolchain

Since it is no longer a flat chip, it is critical to incorporate the mechanical dimensions of the package:

  • First, you need a fully integrated set of ECAD, MCAD, and CAE software to let teams work in sync, and collaborate remotely, so design and thermal issues are detected and solved early.
  • Second, you need a collaborative data management platform to store all the ECAD, MCAD and CAE data to capture the IP needed for reuse and continuous improvement.

Streamlined information sharing

Finally, you need to connect design, production, and manufacturing for a smooth handoff to manufacturing – to squeeze time out of the process to deliver your killer component faster than ever.   

Inside look of a semiconductor